SPI-3 Interface

"The eInfochips SPI-3 Interfaces is fully compliant with POS (Packet-Over-SONET) PHY Level-3 Link Layer interface. It complies with OIF-SPI3-01.0 System packet Interface Level (SPI-3) Interface. The aggregate bandwidth is in excess of 2.488 Gbps supporting OC-48line rates. A four PHY port is supported.

Device Family Support
# Virtex-4 FX
# Virtex-4 LX
# Virtex-4 SX
# Virtex-II Pro

Key Features
# High frequency performance on SPI3 side with an operating frequency exceeding 104 MHz.
# High frequency performance on a custom proprietary interface side with an operating frequency exceeding 100 MHZ.
# Asynchronous FIFO Interface.
# Direct status mode for four PHY ports.
# Programmable FIFO depth and data segment size.
# Performance monitoring includes parity error and FIFO over flow.
# Supports performance-monitoring register with separate Host interface"