Serial ATA (SATA) I/II Host Controller
The so_ip_sata2_hctrl is a soft core implementation of SATA host controller as defined in the SATA specification 2.6. So_ip_sata2_hctrl soft core is fully compliant with the SATA 2.6 specification, and supports both 1.5 Gbit/s and 3.0 Gbit/s data transfer rates.
So_ip_sata2_hctrl core implements physical, link and transport layers. It can use both RocketIO GTP and GTX transceivers to implement physical signaling required by the SATA specification. For the interface with the host processor IP core uses standard PATA interface, and for the interface with the DMA engine simple TX and RX transaction interface.
So_ip_sata2_hctrl core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_sata2_hctrl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. It operates at 37.5 MHz system clock frequency in case of SATA-I (1.5 Gbit/s data transfer rate) mode and at 75 MHz in case of SATA-II (3.0 Gbit/s data transfer rate) mode.
The so_ip_sata2_hctrl core can be evaluated using Xilinx Evaluation Platforms before purchase. This is achieved by using a time-limited demonstration bit file for ML-505/506/507 platforms that allows the user to connect it’s HDD to the SATA-II core and evaluate system performance under different transfer scenarios.
- Fully compliant with the Serial ATA specification revision 2.6
- Simple transaction interface with Host processor and DMA Engine
- 32-bit internal data path
- 8KB FIFO implemented by BlockRAM in both transmit and receive paths
- Low frequency operation
- IP Core system clock of 37.5MHz and PHY clock 75MHz for SATA-I
- IP Core system clock of 75.0MHz and PHY clock 150MHz for SATA-II
- Supports 1.5 Gbit/s and 3.0 Gbit/s data transfer rates
- Supports DMA and PIO commands
- Hardware support for
- Speed auto negotiation for SATA I/II
- 48-bit address set
- Detection of OOB, COMWAKE, K28.5, etc.
- 8b/10b coding and decoding
- CRC generation and checking
- Auto insertion of HOLD primitives
- Native Command Queuing (NCQ)
- Port Multiplier, Port Selector
- First Party DMA (FPDMA)
- CONT primitive support for primitive suppression to reduce EMI
- Implements the shadow register block and the serial ATA status and control registers
- Supports both Virtex5 GTP and GTX RocketIO Transceivers
- Reference design available on ML505/ML506/ML507 Xilinx Evaluation Platfom