Poll

What is your preferred platform for FPGA Design Flow ?
Windows
55%
Linux
36%
Solaris
1%
Mixed
2%
Other
1%
No preference
4%
Total votes: 4783

PT13

PT13 Block Diagram
IP Vendor: 
SingMai Electronics
IP Target Vendor: 
Altera
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Embedded Processing
IP Supported FPGA Device: 
Cyclone
Cyclone II
Cyclone III
Spartan-3
Spartan-3A
Spartan-3A DSP
Spartan-3AN
Spartan-3E
Spartan-II
Spartan-IIE
Spartan/XL
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Virtex
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
Virtex-E
Virtex-E EM
Virtex-II
Virtex-II Pro
IP Description: 

PT13 is an embedded microprocessor IP core intended for simple control operations.

Many applications would benefit from a small degree of local ‘intelligence’ and PT13 is designed for that very function. Whilst most available microprocessor IP cores require external FLASH memory and even external data memory, PT13 is optimized to be completely embedded and use as little FPGA resources as possible.

PT13 uses just 316 logic elements and as little as a single 4kbit ROM block, allowing it to fit in the smallest of FPGAs or even permit multiple instances in the same FPGA.

Yet PT13 can address up to 16kB of program memory and 4kB of user memory or memory mapped I/O peripherals and has over 45 instructions. An editor and assembler allow easy generation of code which is directly compiled into the FPGA download file.

PT13 is ideal in real time control applications allowing such functions as TV tuner control, I2C control, RC5/RC6 decoding, LCD display control, user interface control, closed caption/Teletext decoding and general housekeeping duties to be run without burdening the main control processor. These functions can also be run in very low power applications such as STB/DVD recorder standby conditions or mobile applications.

* Only 316 logic elements.
* Separate program and data memory.
* Up to 16kB of program memory and data memory.
* Memory mapped I/O.
* Instruction cycle time of 1.6MHz at 27MHz input clock.
* 2 accumulators.
* 5 addressing modes.
* Editor with highlighted instruction codes.
* PC based Assembler including source code.
* Example programs.

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook