Single Channel HDLC

"Features
Standards-compliant high-level data link control (HDLC) core
8-bit physical link interface designed for easy interfacing to off-the-shelf framers
Modelware's flexible PluriBus system interface allows easy connection to data FIFO buffers, direct memory access (DMA) controllers, and POS-PHY interface cores
Flexible control inputs with options for internal/external hardwiring and access via a generic microprocessor interface
ASIC and FPGA support
Flag detection and generation
Abort detection and insertion
Zero-bit stuffing and de-stuffing
Selectable transparent mode
Selectable frame filtering based on programmable 8- or 16-bit address field, programmable 8- or 16-bit control field, and programmable 8- or 16-bit protocol field
Selectable frame header insertion (up to 6 programmable octets)
Selectable 16-bit, 32-bit, or no cyclic redundancy check (CRC) generation and monitoring
CRC error generation
Selectable, programmable minimum interframe spacing
Programmable interframe time fill
Supports shared flags
Supports statistics counters for received frames, received short frames, received long frames, received CRC-errored frames, received aborted frames, transmitted frames, and transmitted frames aborted"