Poll

What is your preferred platform for FPGA Design Flow ?:

Sine Cosine Look Up Table

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
DSP - Digital Signal Processing
IP Supported FPGA Device: 
Spartan-3
Spartan-3E
Spartan-II
Spartan-IIE
Virtex
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-E
Virtex-II
Virtex-II Pro
IP Description: 

"The Sine/Cosine Look-Up Table IP core is a drop-in module. It provides a user specified option for table value storage in Distributed/Block Memory. The core supports THETA input widths of 3 to 10 bits for distributed ROM and 3 to 16 bits for block ROM. It supports output Sine/Cosine widths of 4 to 32 bits and negative Sine/Cosine outputs. The core automatically selects from quarter wave storage and 360 degree wave storage to create the optimum implementation. It has a variable pipelining option to improve the overall clock rates.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Virtex-E

Virtex

Spartan-3E

Spartan-3

Spartan-IIE

Spartan-II"

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