Poll

What is your preferred platform for FPGA Design Flow ?:

SDLC Controller

IP Vendor: 
CAST, Inc.
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Acex 1K
Apex 20KC
Apex 20KE
Cyclone
Flex 10KE
Stratix
Stratix II
IP Description: 

"The CAST synchronous data link communication (SDLC) controller's operation is similar to that used in the Intel 8XC152 global serial channel (GSC) working in SDLC mode under the control of the CPU. Special function registers and three interrupt sources facilitate communication with the CPU. This feature allows the SDLC controller to be easily integrated into any CPU megafunction.

The design is strictly synchronous with positive-edge clocking, has no internal tri-states, and has a synchronous reset.

Features
Based on the 8XC152 GSC
Single- and double-byte address recognition
16-bit & 32-bit frame check sequence
Non-return-to-zero (NRZ) & non-return to zero inverted (NRZI) data encoding
Automatic bit stuffing & stripping
Three-byte-deep receive & transmit first-in first-out buffers (FIFOs)
Full- or half-duplex operation
Variable baud rate
External or internal transmit/receive clock"

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