What is your preferred platform for FPGA Design Flow ?:


IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Cyclone II
Cyclone III
Hardcopy II
Stratix GX
Stratix II
Stratix II GX
IP Description: 

Support for multiple serial digital interface (SDI) standards (see Table 1)
Transmitter includes:
Cyclical redundancy check (CRC) encoding (high definition (HD) only)
Line number (LN) insertion (HD only)
Word scrambling
Receiver includes:
CRC decoding (HD only)
LN extraction (HD only)
Framing and extraction of video timing signals
Word alignment and descrambling
Easy-to-use IP Toolbench interface
Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Support for OpenCore Plus evaluation
General Description
The Altera® SDI MegaCore® function implements a receiver, transmitter, or full-duplex standard definition (SD) at HD, SD, or triple rate.

The Society of Motion Picture and Television Engineers (SMPTE) have defined an SDI that video system designers widely use as an interconnect between equipment in video production facilities.

The SDI MegaCore function can handle the following SDI data rates:

270 megabits per second (Mbps) SD SDI, as defined by SMPTE259M-1997 10-Bit 4:2:2 Component Serial Digital Interface 1.485/1.4835 gigabits per second (Gbps)
HD SDI, as defined by SMPTE292M-1998 Bit-Serial Digital Interface for High Definition Television Systems
Preliminary support for SDI 3Gbps, as defined by SMPTE425M-2006 3Gb/s Signal/Data Serial Interface – Source Image Format Mapping
Preliminary support for dual-link SDI, as defined by SMPTE372M-Dual Link 1.5Gb/s Digital Interface for 1920x1080 and 2048x1080 Picture Formats
Triple rate SDI that switches between 270 Mbps and 1.485/1.4835 Gbps"

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