RLDRAM Memory Controller
"The Denali RLDRAM Memory Controller IP core is optimized for Xilinx FPGAs by Avnet Design Services. The core is configured for 64-bit data access. Data capture and clocking are implemented using the advanced features of the FPGA's Digital Clock Manager (DCM). When used with the included layout and pinout guidelines, the design provides a data capture margin of approximately 400 ps. The controller supports all the native functions of the RLDRAM memory devices from Infineon and Micron. Seperate command and data queues keep memory bandwidth to a maximum and user programmable mode registers can be used to tune access parameters to match the requirements of the users back end interface. Internal functions like self refresh and power down are supported to further simplify the design.
Device Family Support
Utilizes the proven Denali DatabahnÃƒÂ¢Ã¢â‚¬Å¾Ã‚Â¢ Memory Processor
200 MHz DDR operation (400 Mbps/pin)
Pipelined queue based interface"