Poll
RLDRAM II Controller
"Features
Support for industry-standard RLDRAM II components
Common I/O (CIO) and separate I/O (SIO) device support
Flexible and robust design
Nonmultiplexed addressing
Datapath generation
Data strobe signal (DQS) and non-DQS capture modes
Easy-to-use IP Toolbench interface and automatic constraint generation
IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
General Description
The RLDRAM II Controller MegaCore® function handles the complex aspects of using RLDRAM IIâ€â€Âinitializing the memory devices and translating read and write requests from the local interface into all the necessary RLDRAM II command signals.
The RLDRAM II controller is optimized for Altera® Stratix® III, Stratix II, Stratix GX, and HardCopy® II devices. The advanced features available in these devices allow you to interface directly to RLDRAM II devices.
IP Toolbench generates the following items:
A testbench, which instantiates the example design
A synthesizable example design which instantiates the following modules:
RLDRAM II controller:
Encrypted control logic, which takes transaction requests from the local interface and issues writes, reads, and refreshes to the memory interface
A clear-text datapath
Example driverâ€â€Âgenerates write, read and refresh requests and outputs a pass_fail signal to indicate that the tests are passing or failing
System phase-locked loop (PLL)â€â€Âgenerates the RLDRAM II controller clocks
Delay locked loop (DLL)â€â€Âinstantiated in DQS mode and generates the DQS delay control signal for the dedicated DQS delay circuitry
Optional fedback clock PLLâ€â€Âinstantiated in non-DQS mode and generates a capture clock for the datapath read capture and logic path"
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