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Reed-Solomon Encoder

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Acex 1K
Apex 20KC
Apex 20KE
Apex II
Flex 10KE
IP Description: 

"Features
Configurable solution for high data rate Reed-Solomon encoding
Supports a range of standards, including European Telecommunication Standards (ETS) 300-421 and ETS 300-429.
Single implementation supports any valid block length
Processes both burst and continuous data
Supports high-speed applications (up to 400 Mbps)
Symbol wide input and output, clocked by single symbol rate clock (higher rate clocks, if available, can be used to reduce gate count)
Low latency implementation: two symbol clock cycles
Simple function interface allows easy integration into larger systems

Description
The Amphion Reed-Solomon encoder megafunction provides compact, high-performance solutions for a wide range of applications.

The European digital video broadcast (DVB) standards provide system requirements for the broadcast of Motion Pictures Expert Group (MPEG)-2 transport packets via, for example, cable or satellite channels. Reed-Solomon error correction coding techniques are employed on the 188-byte MTS packets, with the capability to correct eight errors per transport packet. This correction requires the use of 16 parity symbols per MTS packet, resulting in a shortened Reed-Solomon codeword of N = 204, K = 188 (N is the number of symbols per codeword, K is the number of information symbols).

Amphion offers a range of Reed-Solomon encoder megafunctions, capable of operating up to 400 Mbps on Altera complex programmable logic devices (CPLDs). This megafunction is designed specifically for the requirements of the DVB standards.

The Reed-Solomon encoder megafunction assumes only the availability of a symbol rate clock and all operations in the encoder are timed with this clock. If a higher rate clock—for example a bit rate clock—is available, the clock can be used to reduce the gate count of the encoder."

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