Poll

What is your preferred platform for FPGA Design Flow ?:

RapidIO

IP Vendor: 
Altera
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Cyclone II
Cyclone III
Hardcopy II
Hardcopy Stratix
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
Physical layer features
1×/4× Serial
Stratix® II GX and Stratix GX support, including 1× and 4× up to 3.125 Gbaud
Support for Cyclone series, Stratix series and HardCopy® series with an XGMII-like interface to a high-speed full-duplex, serializer/deserializer (SERDES) transceiver
8-bit Parallel
Stratix series, HardCopy series, and Stratix GX support
Transport layer features
Supports multiple logical layer modules
Supports 8-bit device identities (IDs)
Device IDs, addressable capability registers (CARs), and command and status registers (CSRs) eliminate hop-count handling and CRC recomputing
Capability registers (CARs) and command and status registers (CSRs)
Maintenance master and slave logical layer module
I/O master and slave logical layer module
Doorbell (Type 10 packet) support
Compliant with RapidIO Trade Association, RapidIOTM Interconnect Specification, Revision 1.3

Part 1: Input/Output Logical Layer Specification
Part 2: Message Passing Logical Layer Specification
Part 3: Common Transport Specification
Part 4: Physical Layer 8/16 LP-LVDS Specification
Part 6: Physical Layer 1×/4× LP Serial Physical Layer Specification
Easy-to-use MegaWizard® Plug-In interface
Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
General Description
The RapidIO interconnect—an open standard developed by the RapidIO Trade Association—is a high-performance packet-switched interconnect technology designed to pass data and control information between microprocessors, digital signal processors (DSPs), communications and network processors, system memories, and peripheral devices."

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