What is your preferred platform for FPGA Design Flow ?:

LMS Filter IP Core

IP Vendor: 
Prosynaptech, Inc.
IP Target Vendor: 
IP Code Language: 
IP Type: 
IP Category: 
DSP - Digital Signal Processing
IP Supported FPGA Device: 
Cyclone II
Cyclone III
Stratix II
Stratix III
IP Description: 

The LMS Filter (least mean squared error adaptive filter) IP Core implements both the traditional non-normalized and normalized LMS filters. The core supports delayed update (a feature that enables higher throughput). This IP core can function up to 6 MSPS for short bit widths and filter lengths. Furthermore, sustained performance up to 20 MSPS is achievable with delayed update. Reference the examples at the Prosynaptech website for the approximate resource usage and performance in your application.

Additional Features:
* LMS, NLMS, and DLMS filtering
* Real and complex data
* Pre-compiled simulation libraries
* Customizable resource and performance trade-off
* Supports recent Altera Cyclone and Stratix devices
* Configurable Avalon interface
* Parameterizable bit widths and binary point locations

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook