What is your preferred platform for FPGA Design Flow ?:

Auto IP System v1.0

IP Vendor: 
Prosynaptech, Inc.
IP Target Vendor: 
IP Code Language: 
IP Type: 
IP Supported FPGA Device: 
Arria GX
Cyclone II
Cyclone III
Stratix GX
Stratix II
Stratix II GX
Stratix III
IP Description: 


  • Compact and highly pipelined design: typical 32-bit Cyclone III FPGA operations at 160 MHz with less than 1500 LEs.

  • Operates with streaming input and output interfaces and/or as a memory mapped slave.

  • Hardware state machine: memory bits are only used for data/variables and I/O buffering.

  • System automatically converts all operations to scalar and handles fixed binary-point positioning, reducing hardware design knowledge required.

  • Processes multiple independent data streams (or just one) up to 500 kSPS. Operate many PID control channels or apply smoothing filters to many input sensors using just one core.

  • Selectable equation processing concurrency speeds matrix based calculations by operating on multiple column/row positions simultaneously with only minimal increases in hardware usage.

  • Pre-compiled VHDL testbench and TCL simulation model to generate and test data sets.

  • Try before you buy. Free 45 day evaluation available.



This product-as-a-service provides customizable templates to let users immediately generate IP cores for FPGAs (usable in Altera SOPC Builder) or tailor them to their needs all online through the website. The system implements any set of scalar, vector, or matrix equations using the basic math operators. Developed to operate on multiple data streams up to 500 kSPS (total; varies by the length and complexity of the equations set), this system is ideal for microcontroller offload, independent multichannel applications like controls or sensor data filters, and basic matrix coprocessing. Templates are available for PID control, IIR/FIR Filters, histograms, audio equalizer, and many others.



The Auto IP System generates custom IP Cores based on a hardware state machine and flexible arithmetic core to implement any basic math scalar, vector, or matrix equation set.


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