POS-PHY Level 4

"Features
Stratix® III, Stratix II, Stratix II GX , and HardCopy® II device family support at up to 1,040 Mbps, including integrated dynamic phase alignment (DPA) hardware module
Stratix GX device family support at up to 1,000 Mbps, including integrated DPA hardware module
Stratix device family support at up to 840 Mbps
Cyclone series of device families support at up to 250 Mbps (32-bit data path width variations only)
Configurable data path width—affecting the MegaCore® function size and speed—for various performance requirements and applications:
128 bits
64 bits
32 bits (quarter rate)
Supports up to 256 ports
Fixed start of packet (SOP) alignment to the most significant byte lane eases subsequent packet processing
First-in first-out (FIFO) buffer status management and indications
Configurable FIFO buffer modes
Option to select single or multiple clock domain Atlanticâ„¢ FIFO buffering
Optional Atlantic interface width
Optional parity protection across Atlantic buffer memories
Optional run-time programmable calendar length, burst size, and threshold levels
Asymmetric ports and hitless bandwidth reprovisioning
Error detection and handling
Protocol checking—SPI-4.2 datapath state machine check and repair
Atlantic FIFO buffer overflow handling
Status framing hysteresis (good and bad thresholds)
DIP-4 hysteresis (good and bad thresholds)
Easy-to-use IP Toolbench interface
Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Support for OpenCore Plus evaluation
I-Tested Certification
Compliant with all applicable standards, including:
Optical Internetworking Forum (OIF), System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices, OIF-SPI4-02.0, January 2001.
PMC-Sierra Inc., POS-PHY Level 4 A Saturn Packet and Cell Interface Specification for OC-192 SONET/SDH and 10 GB/s Ethernet Applications, Issue 5 (Draft): June 2000.
Altera Corporation, Atlantic Interface Specification.
Altera Corporation, Avalon® Streaming Interface Specification.
General Description
The packet over SONET/SDH physical layer (POS-PHY) Level 4 interface, first developed by the SATURN Development Group, was later adopted by the Optical Internetworking Forum (OIF) as the System Packet Interface Level 4—Phase 2 (SPI-4.2). Therefore, POS-PHY Level 4 and SPI-4.2 are synonymous.

The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for high-speed cell and packet transfers between physical (PHY) and link layer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS solution), and can be a PHY-link, link-link, link-PHY, or PHY-PHY connection in multi-gigabit applications, including: asynchronous transfer mode (ATM) and packet over SONET/SDH (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel Gigabit and Fast Ethernet."