XpressLite2 for Altera Stratix II GX

Our XpressLite2 endpoint IP and its acclaimed EZDMA user interface will integrate rapidly and seamlessly into your design

IP Features and Deliverables

• PCI Express® IP core in synthesizable Verilog and VHDL RTL encrypted or clear source code
  • Compliant with the PCI Express® Base Specification, revision 2.0.1
    • Backwards compatible to the PCI Express® Base Specification, revision 1.1
  • Supports Native and Legacy Endpoint
    • x1, x4, x8
    • 1 Virtual Channel (VC)
  • Includes Physical, Data Link, Transaction, and EZ Application layers
    • Optimized for high throughput and minimal latency
  • PIPE interface to PHY
    • 16-bit/125Mhz (x1, x4)
    • 8-bit/250Mhz (x8)
  • Maximum payload size up to 2KB
  • Number of outstanding read requests: up to 16
  • Up to 6 BARs plus expansion ROM
  • Full Power Management
  • DMA-based user's interface (EZDMA)
    • Up to 8 DMA channels
    • Scatter-Gather support with host based descriptors
    • Integrated DMA arbitration optimized for maximum throughput
• PCI Express® 2.0 Testbench simulation libraries
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• PCI Express® IP core simulation models
  • For Cadence NC-Sim, Mentor Modelsim, Synopsys VCS
• PIPE wrappers and Physical Coding Sub-layers (PCS)
  • For the supported Altera FPGA families with embedded PCI Express® 2.0 PHY/SerDes
• Configuration assistant GUI (Wizard)
  • Multi-platform JAVA based
• Endpoint reference design
  • Synthesizable Verilog and VHDL RTL source code
  • Simulation environments and scripts
  • FPGA synthesis/PAR environments and scripts
• Software Design Environment
  • 32-bit/64-bit Linux, 32-bit Windows XP PCI Express® device driver binary
    • Source code option available
  • C source code API
  • PCI Express® GUI tools and source code (C++, Java)
• Complete documentation