DMA for PCIe Integr. Block

March 26, 2009 - 2:47am — sales@plda.com

IP Vendor:

PLDA

IP Target Vendor:

Xilinx

IP Type:

Design

IP Category:

Bus Interface and IO

IP Supported FPGA Device:

Virtex-5 LXT

Virtex-5 SXT

http://www.plda.com/prodetail.php?pid=156

IP Description:

PLDA EZ DMA IP for Xilinx Virtex 5 is designed for those with little or no experience with PCI ExpressÂ® or experienced designers looking for an easy to use yet robust PCI ExpressÂ® v1.1 interfacing solution for Xilinx Virtex 5 FPGA. The EZ DMA IP for Xilinx Virtex 5 wraps around Xilinx PCI ExpressÂ® Endpoint Block Plus and adds PLDA renowned EZ DMA interface providing multi-channel DMA capability with scatter-gather support. The EZ DMA interface is the native user interface on PLDA's XpressLite and XpressLite2 IP, and is backward compatible to PLDA's PCI and PCI-X IP user interfaces.

What's unique about our IP?

* IP is provided in both Verilog and VHDL RTL and enables Verilog-only and VHDL-only design flows
* A comprehensive event-based/procedure-based Testbench is provided with our IP which allows powerful system-level functional verification
* We deliver comprehensive reference designs and state-of-the-art FPGA based prototyping boards to get you started and to let you prototype your designs in hardware
* Our IP package includes a comprehensive Software Design Environment with license-free device drivers, API, and example GUI applications with source code
* We offer professional services to quickly and reliably customize our IP to fit your specific requirements
* Our IP customization GUI (Wizard) allows you to create a custom instance of the IP with only the required feature set; any disabled feature will be synthesized out, allowing for resource optimization
* A free, risk-free evaluation program that includes the same deliverables and technical support as the licensed IP
* Fast and accurate, industry acclaimed technical support provided by the IP designers

The EZ DMA IP Core supports Xilinx Virtex 5 LXT and Virtex 5 SXT.
The IP Core supports Xilinx Endpoint Block Plus in x1, x4 and x8

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DMA for PCIe Integr. Block

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