What is your preferred platform for FPGA Design Flow ?:

PCI-X Master/Target Core 32/64-Bit

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Apex II
Cyclone II
Stratix II
IP Description: 

Standards compliance
PCI-X addendum to PCI local bus specification (revision 1.0b)
PCI power management (revision 1.1)
General features
32- or 64-bit PCI-X master/target interface
Supports bus speeds up to 133 MHz
Multi-function core can implement up to four independent functions
Full-support 64-bit addressing
Built-in support for in-site programming through Joint Test Action Group (JTAG) interface
Supports all required and optional type 0 configuration registers
Configuration space can be mapped in a base address
Up to six base address registers (BARs) plus expansion ROM
Up to 32 user-defined configuration registers
Data transfer
Supports burst memory and I/O transfers with zero wait-state insertion
Supports all memory and I/O commands
Supports interrupt acknowledge cycles in target mode
Can insert wait-states and generate all types of terminations
Direct memory access (DMA)
Up to four independent DMA channels with rotating priority
Flexible back-end interface can directly connect first-in first-out (FIFO) devices
Can generate all existing PCI-X commands
Optional scatter-gather support
64-bit data transactions are dynamically negotiated
Split transactions are fully supported on all DMA channels
Device families targeted
Stratix devices; -5 and -6 speed grades
APEX II devices
Device resource utilization
3,500 logic elements (LEs) (typical)
100 I/O pins
Memory usage: none"

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