Poll

What is your preferred platform for FPGA Design Flow ?:

PCI Target: 32-bit

IP Vendor: 
Lattice
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

Features

Available as 32/64-Bit PCI Bus and 32/64-Bit Local Bus
Available in Master/Target and Target Versions
PCI SIG Local Bus Specification, Revision 2.2 Compliant
64-Bit Addressing Support
Capabilities List Pointer Support
Parity Error Detection
Up to Six Base Address Registers (BARs)
Expansion ROM BAR Support
Fast Back-to-Back Transaction Support
Supports Zero Wait State Transactions
Special Cycle Transaction Support
Customizable Configuration Space
Up to 66MHz PCI
Fully Synchronous Design"

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