What is your preferred platform for FPGA Design Flow ?:

PCI-PCI Bridge

IP Vendor: 
Eureka Technology
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Acex 1K
Apex 20KC
Apex 20KE
Flex 10KE
IP Description: 

Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1
Designed for programmable logic device (PLD) and ASIC implementation in various systems environments
Fully static design with edge-triggered flip-flops
Independent asynchronous PCI clocks on primary and secondary bus
Converts bus transactions between primary bus and secondary bus
Combines bus master and target functions on both primary bus and secondary bus
Dual write buffer on each direction supports posted memory write
Supports prefetchable and non-prefetchable memory read
Delays transaction processes I/O read/write, configuration read/write, and memory read transactions
Supports target retry, disconnect, master abort, and target abort terminations
Includes all PCI-to-PCI bridge specific configuration registers

The 32-bit PCI-to-PCI bridge is designed for interfacing between the primary PCI bus and the secondary PCI buses. The PCI bridge consists of a bus master, bus target, and target functions on the primary PCI bus. The secondary bus consists of a bus master, bus target, and configuration initiation functions.

The bridge has a dual write buffer on each bus interface to post memory write. The all-memory first write and second write invalidate data and are posted in the write buffer. The transaction is first completed in the original bus by the PCI bridge as a target to the transaction. It then writes to the destination bus. The dual write buffer allows the original bus to post a second write request to the bridge while the first write request is being processed.

The bridge functions as a bus master on the destination bus. All different types of transfer termination are handled by the core. If a transfer is retried or disconnected by the target in the destination bus, the bridge automatically restarts the transfer until all posted data is written. Bus request, bus parking, parity detection, and generation all are handled by the core.

This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL as well as netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements."

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook