Poll
What is your preferred platform for FPGA Design Flow ?
Windows
54%
Linux
37%
Solaris
1%
Mixed
3%
Other
1%
No preference
4%
Total votes: 3278
PCI Master/Target: 64-bit
IP Vendor:
Lattice
IP Target Vendor:
Lattice
IP Type:
Design
IP Category:
Bus Interface and IO IP Description:
Features
Available as 32/64-Bit PCI Bus and 32/64-Bit Local Bus
Available in Master/Target and Target Versions
PCI SIG Local Bus Specification, Revision 2.2 Compliant
64-Bit Addressing Support
Capabilities List Pointer Support
Parity Error Detection
Up to Six Base Address Registers (BARs)
Expansion ROM BAR Support
Fast Back-to-Back Transaction Support
Supports Zero Wait State Transactions
Special Cycle Transaction Support
Customizable Configuration Space
Up to 66MHz PCI
Fully Synchronous Design








