What is your preferred platform for FPGA Design Flow ?:

PCI Express x1 Lane

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Hardcopy II
Stratix GX
Stratix II
Stratix II GX
Stratix III
IP Description: 

Suitable for endpoint applications (including nontransparent bridges) with x1, x4, and x8 lane support
PCI Express 1.1 compliance
Support on Altera's PCI Express Development Kit, Stratix® II GX Edition
Configurable maximum payload (up to 2 Kbytes and configurable retry buffer (up to 16 Kbytes)
Optional end-to-end cyclic redundancy code (ECRC) generation/checking and advanced error reporting (AER)
Flexible reference clock support (100, 125, or 156.25 MHz)
Easy-to-use MegaWizard® Plug-In interface to configure the MegaCore® functions and testbench
Multiple example designs to jump start customer designs
General Description
The PCI Express Compiler generates customized PCI Express MegaCore functions you can use to design PCI Express endpoints, including nontransparent bridges, or truly unique designs combining multiple PCI Express components in a single Altera® device. The PCI Express MegaCore functions are PCI Express Base Specification Revision 1.1 or PCI Express Base Specification Revision 1.0a compliant, and implement all required and most optional features of the specification for the transaction, data link, and physical layers. Figure 1 illustrates a typical PCI Express application."

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