Poll

What is your preferred platform for FPGA Design Flow ?:

PCI Express x1 Endpoint - Optimized for LatticeECP2M

IP Vendor: 
Lattice
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

PCI Express (PCIe) is a high-performance, scalable, chip-to-chip interconnect standard for a broad range of computing and communications platforms. It incorporates a serial packet-based protocol along with a switch-based topology to deliver high speed, while maintaining complete software compatibility with the existing base of operating systems, PCI drivers, and software.

Lattice's PCIe x1 Endpoint IP core provides a complete x1 endpoint solution that includes the transaction, data link, and physical layers, as well as the electrical SerDes interface. The core is optimized to work with the Physical Coding Sublayer (PCS) and SerDes interface of the new LatticeECP2M device family, enabling a complete, single-chip solution ideally suited for a wide set of applications requiring high-performance, high-integration, and low-cost. Lattice also provides the IPexpress and SerDes configuration tools as part of its ispLEVER design package to to enable quick customization of the core and the SerDes interface. Combining the core and tools with the LatticeECP2M PCI Express Evaluation Board provides a powerful solution that allows designers to quickly deploy PCIe solutions rather than focus on the specifications, resulting in fast time-to-market.

Features
Top Level IP Support
250 MHz Reference Clock Input
125 MHz, 16-bit Data Path User Interface
Creates TLPs without ECRC or Sequence Number during Transmit
Receives Valid TLPs without Sequence Number during Receive
Credit Interface for Transmit and Receive and for PH, PD, NPH, NPD, CPLH, CPLD Credit Types
Higher Layer Control for Link Training and Status State Machine (LTSSM) via Ports
Access to Select Configuration Sapce Information via Ports
Compliant to PCI-SIG PCI Express 1.0a Base Specifications
Configuration Space Support
PCI-Compatible Type0 Configuration Space Registers
Power Management Capability Structure Registers
MSI Capability Structure Registers
PCI Express Capability Structure Registers
Extend Capabilities Register for Virtual Channel Support
Transaction Layer
Supports all types of TLPs (Memory, I/O, Configuration, and Message)
Virtual Channel (VC) Support of 1-8 Channels
Flow Control Enforcement with Separate Credit Interface per VC
Optional ECRC Generation/Checking
Power Management User Interface

Data Link Layer
Data Link Control and Management State Machine
Flow Control Initialization
Ack/Nak DLLP Generation/Termination
Power Management DLLP Generation/Termination through simple user interface
LCRC Generation/Checking
Sequence Number Appending/Checking/Removing
Retry Buffer and Retry Management
Credit Availability Calculation and Reporting
PHY Layer
2.5 Gbps Electrical Interface
Serialization and De-serialization (SerDes)
8b/10b Symbol Encoding/Decoding
Link State Machine for Symbol Alignment
Clock Tolerance Compensation supports +/- 300 ppm
Framing and Application of Symbols to Lanes
Data Scrambling
Link Training and Status State Machine (LTSSM)
Electrical Idle Generation
Receiver Detection
TS1/TS2 Generation/Detection
Land Polarity Inversion
Higher Layer Control to jump to Define States

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook