What is your preferred platform for FPGA Design Flow ?:

PCI Express

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Stratix GX
Stratix II
IP Description: 

PCI Express Specification 1.0a compliant
4x lane PCI Express core
Suitable for root complex, bridge, switch, and endpoint designs
64-bit, 125 MHz interface
Upstream and/or downstream mode for link initialisation
Up to eight virtual channels (VC)
Configurable receive (RX), transmit (TX) and retry buffer size
Intel PIPE (16-bit mode) compliant
Optional backend interface on user’s clock domain
Supports up to 4 KB data payload size
Supports all message, completion, memory and I/O requests
Highly optimized RX/TX backend interface for maximum effective throughput
Implements type 0 configuration space for endpoint designs
Implements type 1 configuration space for root, switch and bridge designs
Up to 6 BARs plus expansion ROM available for endpoint
All I/O and memory windows implemented for root, switch and bridge
All power management states and associated logic implemented
Supports legacy PCI Power Managment"

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