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PCI Compiler, 32-bit Target

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Cyclone II
Cyclone III
Hardcopy II
Hardcopy Stratix
Max II
Stratix GX
Stratix II
Stratix II GX
Stratix III
IP Description: 

32-bit PCI target
Fully compliant with the timing and functional requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0
66-MHz compliant when used with 66-MHz PCI-compliant Altera® devices
Extensively tested in hardware
SOPC Builder-ready general purpose, full-featured bridge
PCI complexities (retry, disconnect) hidden from user
Hard-coded PCI BAR hit address to Avalon® address translation
Avalon data burst capability
Independent or common PCI and Avalon clock domains
Provides the option for increased PCI read performance by increasing the number of pending reads
Intellectual property (IP) functional simulation models provide cycle-accurate behavioral simulations in industry-standard Verilog HDL and VHDL simulation tools
Open-source PCI testbench provides flexible PCI bus functional models to verify Altera PCI MegaCore® function-based applications in industry-standard Verilog HDL and VHDL simulation tools
Reference designs for popular functionality implemented on the local side of the PCI MegaCore functions, including direct memory access (DMA) engines, data path first-in first-out (FIFO) architectures, and SDRAM interfaces
General Description
Altera's PCI Compiler provides a complete, easy-to-use solution for implementing a PCI interface with Altera programmable logic devices. The PCI Compiler contains the Altera pci_mt64, pci_t64, pci_mt32, and pci_t32 MegaCore functions, and supports both SOPC Builder and MegaWizard® Plug-In design flows. The SOPC Builder design flow allows you to quickly and easily implement a PCI interface into your design. Whether your top priority is high bandwidth, high speed, or a combination of features, you can use the PCI Compiler to meet your system requirements.

Altera’s PCI MegaCore functions are fully tested to meet the requirements of the PCI-SIG PCI Local Bus Specification, Revision 3.0 and Compliance Checklist, Revision 3.0. You can test-drive Altera PCI MegaCore functions using the OpenCore Plus feature to compile, simulate, and hardware test the functions within your custom logic. When you are ready to license a function, contact your local Altera sales representative.

The pci_t32 MegaCore function provides a fully compliant, target-only, 32-bit, 66-MHz PCI bus interface. It is optimized for the Stratix® III, Stratix II, Stratix, Stratix II GX, Stratix GX, HardCopy® II, HardCopy Stratix, Cyclone III, Cyclone II, Cyclone, and MAX® II device families."

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