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PCI Bus Arbiter

IP Vendor: 
Eureka Technology
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Apex 20KC
Apex 20KE
Excalibur
Flex 10KE
Stratix
IP Description: 

"Features
Complies with PCI bus specification 2.2
Designed for programmable logic device (PLD) and ASIC implementation in various system environments
Fully static design with edge-triggered flip-flops
Supports two to any number of bus masters
Bus parking
Fast request-to-grant turnaround time
Quiet cycle during master switch
Master time-out

Description
The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.

The PCI bus arbiter implements either rotating priority or a fixed priority scheme. In the rotating priority scheme, the requestor that is most recently granted the bus receives the lowest priority, while the requestor position next to it receives the highest priority. The remaining requestor receives subsequently lower priority based on its position.

This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize the design according to specific user requirements."

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