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DVB-S modulator

DVB-S modulator
IP Vendor: 
MVD Cores
IP Target Vendor: 
Xilinx
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
Spartan-3A
Spartan-3A DSP
Spartan-3E
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
IP Description: 

Description

The MVD DVB-S core is a drop-in module that includes the following functions:

  • Input data framer from DVB-SPI source (MPEG-TS flow)
  • Modulator
    • Energy dispersal
    • Reed Solomon encoder
    • Enterleaver
    • FEC convolution encoder
  • Programmable RRC filter
  • Flexible Digital Up Converter
  • Modulator for IF output
  • Output for simple DAC (14 bits) or complex DAC (2x16bits)

Features

Ready to use DVB-S compliant modulator core

  • For Virtex-5™, Virtex-4™ and Spartan™-3/E/A FPGAs
  • Flexible input and symbol rates
  • PCR restamping
  • Fully optimized single channel version
  • Single clock (up to125 MHz+ for Spartan-3™,Virtex-4/5™)
  • Dynamically Programmable FEC 1/2, 2/3, 3/4, 5/6, 7/8
  • Symbol rate from 1 to 31.25Msym/s
  • Dynamically programmable DUC
  • Full synthetizable RTL VHDL design (not delivered) for easy customization

The DVB-S modulator modules an MPEG-TS DVB-SPI input into a QPSK output in base band or IF.

 DescriptionThe MVD DVB-S core is a drop-in module for FPGA that includes the following functions:

  • Input data framer from DVB-SPI source (MPEG-TS flow)
  • Modulator
    • Energy dispersal
    • Reed Solomon encoder
    • Enterleaver
    • FEC convolution encoder
  • Programable RRC filter
  • Flexible Digital Up Sampler
  • Modulator for IF output
  • Output for simple DAC (14 bits) or complex DAC (2x16bits)

FeaturesDVB-S (ETS 300 421) Compliant baseband transmitter for Satellite Modem Termination Systems (SMTS)

  • Drop-in module for Virtex-6™, Virtex-5™,Spartan-6™ and Spartan™-3/E/A FPGA
  • Single clock (up to 140 MHz+ for Spartan-3/6™, 180 MHz+ for Virtex-5/6™)
  • Robust SPI input (discarding incorrect input packets)
  • PCR re-stamping
  • Supports programmable symbol rates
  • Programmable 1/2, 2/3, 3/4, 5/6 and 7/8 punctured FEC
  • Baseband or Intermediate frequency output for complex DAC (2 x 16 bits)
  • Single / multi channel
  • Fully synthesisable RTL VHDL design (not delivered) for easy customization
  • Design delivered as Netlist
  • MER > 40dB

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