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Multi Port SDRAM Memory Controller

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Memory Interface and Storage Element
IP Supported FPGA Device: 
Cyclone
Cyclone II
Stratix
Stratix II
IP Description: 

"Features
Supports multiple Avalon® bus interfaces
Optimized for streaming data applications
Supports Avalon pipelined and burst transfers
Fully independent clock domains for memory and Avalon buses
Configurable cache for each Avalon port
Optimized cache controller minimizes memory wait states
Cache controller supports bursting look-ahead read cycles and post-write memory cycles
Auto termination of cache look-ahead prefetch reading cycles on memory write cycles minimizing insertion of wait states
Supports standard SDR and DDR memory devices and modules
Configurable SDRAM data width (8, 16, or 32 bits)
Automatically generates initialization and refresh sequences
Unique independent DDR round-trip capture scheme
SOPC Builder Ready component
Quartus® II reference designs for Altera® Cyclone® and Stratix® development kits
Single and multi-user licensing
Free OpenCore Plus evaluation
Custom versions and non-Avalon configurations available

Description
The Microtronix Multi-port SDRAM Memory Controller intellectual property (IP) core is designed for building high-performance, multi-master streaming data systems. The core allows the system bus architecture to be partitioned and independently clocked for maximum performance. Each port is supported with a data cache which effectively doubles memory bandwidth on cache hits. Cache size can be tailored for either streaming or random access.

The easy-to-use memory controller simplifies memory designs by supporting SDR, DDR, and DDR2 memory devices using a single system bus interface. The core is optimized for Altera Stratix and Cyclone families of programmable logic devices and supplied as a SOPC Builder Ready component. Proprietary data synchronization design features enable maximum system clock rates using low-speed FPGAs and standard memory devices.

The SDRAM Memory Controller handles all memory tasks, including initialization and refresh cycles. The IP core is designed to operate asynchronous of the system clocks. Clocking the IP core at the peak rated frequency as the SDRAM memory maximizes system performance.

The DDR/DDR2 Memory Controller IP uses a unique architecture to capture the high-speed, DDR data from the memory device independent of the memory round-trip. This proprietary technology simplifies memory interface design by removing the need for extra resynchronization clocks and maximizes the performance of the memory system.

The free, 30-day Altera OpenCore Plus evaluation license feature enables you to do the following:

Simulate the behavior of the IP core within your system
Verify the functionality of your design as well as evaluate its size and speed quickly and easily
Generate time-limited device programming files for designs that include the IP core
Program a device and verify the design in hardware
When completely satisfied with the IP core functionality and performance and the design is ready for production, you only need to purchase a license for the IP core."

Comments

FC guest (not verified)
September 28, 2008 - 8:21pm

What is the IP's features

What is the IP's features compared with the other IPs. Such as what's the arbiter priority or how to minimize the collisions.


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