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What is your preferred platform for FPGA Design Flow ?:

MPEG-4 Video Compression Decoder

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
Virtex-II
Virtex-II Pro
IP Description: 

"The AllianceCORE MPEG-4 Video Compression Decoder from 4i2i is a fully pipelined dedicated video compression decoder engine capable of supporting several popular video standards. The core reads an input bit stream (and reference picture) from memory and outputs a decoded picture back to memory. Host processor requirements are minimal and only 6 registers (specifying the frame locations and coding options) need be programmed once at the beginning of each frame. The core requires a single memory component preferably clocked at the same speed as the core itself.The core can generally share this memory with the host or render components with no loss of performance.

Device Family Support
# Virtex-II Pro
# Virtex-II
# Spartan-3

Key Features
# Full MPEG4 short header / H.263 support (partial Simple and Advanced Simple support option)
# Partial MPEG1, MPEG2 support
# Throughput PAL (704x576x25fps) or NTSC (704x480x30fps) @ 58MHz (Revision to 52MHz available shortly)
# Hardware or software Huffman decode and depacketisation
# Minimal host processor requirements
# Single external frame buffer required (> 1 x Frame Size)
# Optional (scaling, noise reduction) post-processing stage"

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