Poll

What is your preferred platform for FPGA Design Flow ?:

MPEG-2 Video Decoder

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
Virtex-II
Virtex-II Pro
IP Description: 

"The MPEG2 decoder is designed to provide high performance solutions for a broad range of motion image applications. This highly integrated application specific virtual component (ASVC) is for standard definition video, compliant with ISO/IEC 13818-2 (MPEG2) and capable of decoding video streams at the Main Profile at Main Level (MP@ML). The CS6651 is at home in mainstream consumer applications and can also decode MPEG1 (ISO.IEC 11172-2 ) bitstreams. The CS6651 is available for Xilinx FPGA's and is handcrafted by Amphion for optimal performance while minimizing power consumption and silicon area.

Device Family Support
# Virtex-II Pro
# Virtex-II
# Spartan-3

Key Features
# Supports progressive scan and interlaced streams
# ISO/IEC 13818-2 (H.262) Compliant; MP@ML, Decodes ISO/IEC11172-2 (MPEG-1) Constrained Parameter bitstreams
# High performance solution for MPEG2 Decoding; supports input bit rates up to 30Mbit/sec, real time decode and display of MP@ML
# Supports PAL and NTSC SDTV resolutions and frame rates
# Bitstream error detection and recovery
# Glueless interface to external SDRAM
# Capable of standalone stream decoding or host CPU controlled operation"

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