Poll

What is your preferred platform for FPGA Design Flow ?:

Motion JPEG Decoder

IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
Spartan-IIE
Virtex-E
Virtex-II
Virtex-II Pro
IP Description: 

"The 4i2i Communications JPEG Decoder performs JPEG decompression in accordance with the Baseline ISO 10918 standard. The core includes a macroblock de-formatter allowing operation with a very simple interface. All address generation and data ordering is done within the core itself. This is combined wIth very efficient use of FPGA resources to create a very cost effective solution in the Xilinx FPGAs.

Device Family Support
# Virtex-II Pro
# Virtex-II
# Virtex-E
# Virtex
# Spartan-3
# Spartan-IIE

Key Features
# Suitable for Motion JPEG or still image applications
# Processes up to 30 CIF frames per second @ 40 MHz
# Macroblock de-formatter supports YUV 4:2:0 and 4:2:2 formats
# Full header parsing - quantization table and image parameter extraction
# Full restart marker support
# PC evaluation board available"

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