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Mixed
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Total votes: 3278

Motion JPEG CODEC (CS6190)

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Cyclone
Cyclone II
Stratix
Stratix II
IP Description: 

"Features
Single sample per clock cycle processing
Fully compliant with the baseline Joint Photographic Experts Group (JPEG) standard
Able to compress and decompress 800-k pixel color images at full frame rate
Fully synchronous operation
One symbol per clock cycle Huffman-decoding capability
No requirement for microprocessor control or pre-processing
Simple first-in first out (FIFO)-like interface for JPEG decoding stream input
Decodes tables and parameter information from JPEG bitstream
Encoding and decoding parameters, such as image size, made available for controlling peripherals, including raster to block converter
Processes images up to 64K by 64K
Support for all interleaved and non-interleaved scans
Half duplex: encode or decode—ideal for non-simultaneous record-then-playback or store-then-retrieve
Bit-rate control for dynamic output rate stabilization
Zero power standby mode"

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