Poll

What is your preferred platform for FPGA Design Flow ?:

MediaLB Device Interface

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Cyclone II
Stratix II
IP Description: 

"Features
MediaLB Device Interface
Based on the OS62400 MediaLB Device Interface Macro from SMSC (Oasis)
MediaLB Device Physical and Link Layer requirements
Command and data transmission
Data reception and RxStatus response transmission
MediaLB lock detection
System channel command handling
3-pin and 5-pin MediaLB Device mode
Up to 15 channels: synchronous, asynchronous, isochronous, contro
124 Bytes of data per frame
256FS / 512FS / 1024FS
Parameterized
Avalon® interface for Nios® II processor

Description
Small but efficient MediaLB Device Interface
Easily integrated into Nios II systems using SOPC Builder
Avalon interface for Nios II processor
Royalty-free
OS81050 module available
Verified on Nios II development boards
Evaluation version available"

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