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Mapper, STM0/OC1, STM1/OC3, STM4/OC12

IP Vendor: 
Aliathon
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3
IP Description: 

"Aliathon's Multi-channel SDH Mapper core provides a flexible, resource-efficient solution for mapping lower order PDH signals into SDH/SONET. The core is ideally suited for STM0, STM1 and STM4, and the core may be replicated in parallel to interface to STM16 and beyond. The core connects to other Aliathon cores to implement complete SDH/PDH solutions.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Spartan-3

Key Features

Generates up to 16 VC payloads. These VCs can be a mix of VC3 and VC4.

Maps TUG3 structures into VC4 and TUG3 structures into VC3 and TUG3.

Maps TUs (TU11, TU12 and TU2) into TUG2. The TU type can be dynamically configured on a per TUG2 basis. TU3 within TUG3 is also catered for, as is VC11 over TU12.

Generates all TU pointers, including the TU3 pointer for TU3 over TUG3.

Inserts all Lower-Order Path Overhead, and calculates BIP-2 (B3 in the case of TU3 over TUG3).

Maps PDH signals into VC and TU payloads. All mappings for TU11, TU12, TU2, VC3 and VC4 are implemented.

Accepts a multi-channel input of up to 336 TU payloads (TU11 over STM4)."

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