Poll
Linear Feedback Shift Register
IP Vendor:
Xilinx
IP Target Vendor:
Xilinx
IP Type:
Design
IP Category:
Basic Logic IP Supported FPGA Device:
Spartan-3
Spartan-3E
Virtex
Virtex-E
Virtex-II
Virtex-II Pro
IP Description:
"The Linear Feedback Shift Register (LFSR) IP core uses feedback to modify itself on each rising edge of the clock. The feedback causes the value in the shift register to cycle through a set of unique values. The parameterizable choices of LFSR length, gate type, LFSR type (Fibonacci or Galois), maximum length logic, and tap positions allow the user to control the implementation and feedback of the LFSR, which in turn, control the sequence of repeating values the LFSR will iterate through.
Included with Xilinx ISE Software
Device Family Support
# Virtex-II Pro
# Virtex-II
# Virtex-E
# Virtex
# Spartan-3
# Spartan-IIE"
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