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BA129 - JPEG 2000 decoder - Sub-frame latency

IP Vendor: 
Barco-Silex
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Arria GX
Stratix III
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
IP Description: 

Capitalizing on its long-term experience with JPEG 2000 hardware coding, Barco Silex offers a large JPEG 2000 portfolio including this compact, real-time hardware decoder engine that is optimized for low-latency video applications. The core architecture offers a flexible and high-speed solution to meet the challenges of high-end broadcast applications. The BA129 is able to sustain up to 180 frames per second of 1080i format, for compressed stream bitrates extending up to 400 megabit per second.

The BA129 core decodes streams that are compliant with the ISO/IEC 15444-1 specification (JPEG 2000) and supports single-tiled frames up to 1080p or larger.
The BA129 is the complement of the BA130 sub-frame latency JPEG 2000 encoder IP, to which it can be directly connected.

The IP core performs the complete video decompression operations of the normalized decoding process:
• Stream parsing and header decoding
• Entropy decoding
• Inverse quantization
• Inverse discrete wavelet transform (IDWT).

The BA129 takes a JPEG 2000 file and generates decoded samples at its output interface with up to 12 bits per color sample. An optional module can be used to generate the video output in real-time, without any buffering, to preserve the low latency performances.

The BA129 IP provides a single-FPGA solution for 720p30-180, 1080i30-180 and 1080p30-90 video modes, with a total pixel-to-pixel latency below 9ms for 1080i/p60, below 5ms for 1080i/p120 and below 3ms for 1080i/p180 when used together with the BA130 encoder.

The flexible FPGA architecture allows the user to build a secure decoder by integrating Barco Silex cryptography IP cores.

Sub-frame latency JPEG 2000 decoder IP

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