What is your preferred platform for FPGA Design Flow ?:

BA411E - Multi-purpose AES crypto engine

Block diagram of BA411E - AES crypto engine
IP Vendor: 
IP Code Language: 
IP Type: 
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Arria GX
Cyclone III
Spartan-3A DSP
Stratix II
Stratix II GX
Stratix III
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
IP Description: 

The BA411E is a multi-purpose AES crypto engine developed, validated & licensed by Barco Silex.

Scalable AES Core
The BA411E includes a generic (ASIC, Actel, Altera, Xilinx) & scalable (32-, 64- or 128-bit internal data path) implementation of the AES algorithm, making the solution suitable for a wide range of low-cost or high-speed applications.

Flexible Wrapper & Suitable Interfaces
With a very flexible wrapper supporting a wide selection of programmable ciphering modes (ECB, CTR, CBC, CFB, OFB, OMAC, CCM & GCM) and several options of data interface (FIFO, DMA, AXI4, …), the BA411E is an easy-to-use solution with predictable resources & performances on ASIC & FPGA.

Optional capabilities
• Interleaved ECB, CTR, CCM & GCM modes for ultra-high performances
• Masking for applications requiring higher level of security - protection against SPA & DPA (Simple/Dual Power Analysis)
• ‘Bypass’ or ‘NULL Cipher’ mode for streaming applications
• Stallable core
• AXI4-Stream & FIFO Interface

Scalable AES crypto engine supporting a wide range of cipher modes like ECB, CBC, CTR, CFB, OMAC, CCM & GCM, giving the best trade-off silicon/performances on ASIC & FPGA.

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook