Poll

What is your preferred platform for FPGA Design Flow ?:

JPEG, Fast color image decoder

IP Vendor: 
Barco-Silex
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Virtex
Virtex-E
Virtex-II
IP Description: 

"The Barco-Silex FASTJPEG_C color JPEG decoder core is intended for high-speed decoding of color, multi-scan, or gray-scale images coded with the ISO/IEC 10918-1 baseline coding standard. The decoder supports all features of the baseline standard including restart markers and full header parsing. It can decode abbreviated-format or full-format images, by automatically extracting the quantization and entropy tables. Its autonomous behavior, its simple FIFO-like interfaces, and its 100% synchronous structure allows easy integration into a complex system with minimum effort.

Device Family Support
# Virtex-II
# Virtex-E
# Virtex

Key Features
# Baseline ISO/IEC 10918-1 JPEG compliance
# Supports color, multi-scan, and gray-scale"

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