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JPEG, Decoder

IP Vendor: 
CAST, Inc.
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
Spartan-3E
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II
Virtex-II Pro
IP Description: 

"The AllianceCORE JPEG, Decoder (JPEG_D), from CAST implements a high-performance image decoder that complies with the baseline ISO/IEC 10918-1 JPEG standard. One of the fastest available JPEG cores, the JPEG-D provides a high-performance solution for a variety of image and video decompression applications. It can, for example, decode 16:9 HDTV, 1920x1152, 4:2:0. In addition to processing baseline JPEG streams, the core can decompress non-standard motion JPEG streams. It can also be enhanced with an optional IDCT block that enables down-scaling in the frequency domain, a feature that allows decompression at various resolutions from the same compressed stream. The core includes FIFO-like pixel and stream input/output interfaces, and other standard interfaces (e.g. AMBA) are also available. The core is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a software bit-accurate model that facilitates system on chip verification.

Device Family Support
# Virtex-4 FX
# Virtex-4 LX
# Virtex-4 SX
# Virtex-II Pro
# Virtex-II
# Spartan-3E
# Spartan-3

Key Features
# Programmable Huffman Tables (2 DC, 2 AC) and quantization tables (4)
# Up to 4 color components (optionally extendable to 255 components) and any image size up to 64k x 64k
# Motion JPEG decoding; Decompressing at various resolution via downscaling in the frequency domain (optional)
# Supports all possible scan configurations and all baseline JPEG formats for input/output data
# Stand alone operation
# Automatic self-programming by headers parsing
# Broadcasting of decoded image parameters for controlling peripherals such as raster to block converter"

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