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What is your preferred platform for FPGA Design Flow ?:

IPX-AES: AES Symmetric Security range (AES encryption / AES decryption)

IP Vendor: 
intoPIX s.a.
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3
Virtex-4 LX
Virtex-4 SX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
IP Description: 

The IPX-AES Module is
an encryptor / decryptor core range that efficiently implements in FPGA
the Advanced Encryption Standard as specified in the Federal Information
Processing publication FIPS-197 of the National Institute of Standards
and Technology. The IPX-AES module can be customized to ensure its optimization
for a wide range of specific applications with a design architecture
that can be adapted to support from low up to very high bit-rates. Its
flexibility allows combining several functions and operating modes on
very small footprints.

Key features:

  • AES Data and Key sizes : 128
    bits/ 256 bits
  • Functions : Decryption / Encryption
    / Encryption-Decryption / Bypass
  • Data-stream handling : Single
    or Multiple streams
  • Operation modes : ECB, CBC,
    CTR, CFB, OFB
  • Data and key bus widths :
    32 bits, 128 bits, 256 bits
  • Signal clock with asynchronous
    reset :  1
  • Simple external interface
    :  Yes
  • Modules : Looped or 
    Unrolled
  • Pipelined :  Pipelined
    / Un-Pipelined
  • Bit rate :  From 350
    Mbit/s up to 20 Gbit/s

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