Poll

What is your preferred platform for FPGA Design Flow ?:

Inverse Discrete Wavelet Transform (IDWT)

IP Vendor: 
Barco-Silex
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Hardcopy Stratix
Stratix
Stratix II
IP Description: 

Features
Compliant with ISO/IEC 15444-1 Information Technology: JPEG2000 Image Coding System
2D recomposition with a programmable number of up to 5 recomposition levels
Programmable lossless integer 5/3 or lossy floating point 9/7 filter
Periodic symmetric border extension (according to JPEG2000 standard)
Compact lifting scheme architecture with successive horizontal and vertical 1D recompositions
16-bit data path; fixed point 9/7 approximation
Fully configurable tile size from 1 x 1pixel to up to 128 x 128 pixels; configurable tile offset
Features an internal tile buffer for increased performance
Easy slave coefficient interface through direct write access into internal tile buffer (SRAM type) and simple addressing of sub-bands to be placed in tile buffer
Configurable pixel depth and sign up to 16 bits (practically limited to 12 bits for 5/3; 10 bits for 9/7)
High-speed pixel interface allowing transfer of 1 pixel per clock cycle on an entire tile
Easy master pixel interface through simple synchronous protocol
Efficient pipelined architecture
Fully synchronous design for easy integration with provided multicycle definitions for increasing performance
Single clock design

Description
Figure 1 illustrates a simplified block diagram of the BA114IDWT intellectual property (IP), showing the internal modules and the interfaces. The BA114IDWT IP is a tile-level 2D inverse discrete wavelet transform (IDWT) engine recomposing a rectangular tile of any size up to 128 x 128 pixels from multiple frequency sub-bands. The BA114IDWT pixel interface can output an entire tile at high speeds with no interruption.

The core handles up to five multiple re-compositions internally. It reads the various sub-bands from its internal tile buffer where data has been previously stored through the coefficient interface by simply addressing the tile buffer. Sub-band data is arranged to facilitate sub-band access.

In addition to the coefficient interface, the configuration interface specification of the parameters is used for recomposing the tile. This eases the integration of the wavelet core into a processing chain where recomposition parameters come from a prior process. If needed, the configuration interface can easily be driven by a CPU.

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook