Poll

What is your preferred platform for FPGA Design Flow ?:

Interleaver/De-interleaver

IP Vendor: 
Lattice
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
DSP - Digital Signal Processing
IP Description: 

"Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fading. The interleaver rearranges input data such that consecutive data are split among different blocks. At the receiver end, the interleaved data is arranged back into the original sequence by the de-interleaver. As a result of interleaving, correlated noise introduced in the transmission channel appears to be statistically independent at the receiver and thus allows better error correction.

The Lattice Interleaver/De-interleaver IP Core supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix. The interleaved data is obtained by reading the columns of the matrix. Convolutional interleaving feeds the input data to a number of branches, each of which has a shift register with pre-defined length. The output data is taken from the branch outputs. Lattice's Convolutional Interleaver/De-interleaver IP Cores are compliant with ATSC and DVB standards, while the Rectangular Interleaver/De-interleaver is compliant with IEEE 802.16a standard."

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