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PCI Express Scatter/Gather DMA controller
IP Vendor:
Intensys
IP Target Vendor:
Xilinx
IP Code Language:
VHDL
IP Type:
Design
IP Category:
Bus Interface and IO IP Supported FPGA Device:
Virtex-5 FXT
Virtex-5 LXT
Virtex-5 SXT
IP Description:
Features:
- Up to 32 bidirectional DMA channels
- Up to 32 simultaneous read requests
- DMA transfer size from 1 Byte up to 4GByte per channel
- Byte aligned transfer address
- Integrated arbiter with round robin algorithm
- “Completion streaming” mode of memory reading
- Simple FIFO data interface without performance impact
- Flexible control interface
- Host-based and device-based scatter-gather support per channel
- Simple slave memory interface
- Test firmware for Xilinx ML50x boards
Benefits:
- Shortest design cycle by hiding the complexity of Hard PCIe block
- Customization to fit specific customer requirements
- Highest performance
- Low cost
Deliverables:
- Netlist for bus master and slave controller, VHDL source code for connection logic
- Xilinx ML50x reference design with DMA throughput demo and exhaustive transfers tests
The PCIE-SGDMA IP is a DMA controller designed for the Xilinx Virtex- 5 LXT/SXT/FXT/TXT built-in PCIe hard blocks in x1 x4 and x8 lanes.
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