TCP Offload SOC with GEMAC+AMBA+PCIe

•Ideal for high performance and mid performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications

•Less than 4000 Xilinx slices, Altera ALMs or 150,000 ASIC gates + on-chip memory

•Fully integrated 100 M bit/1-G bit high performance EMAC.

•Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance.

•Hardware implementation of TCP/IP stacks’ control plane and data plane.

•Hardware implementation of ARP protocol.

. ARP table creation, deletion management (optional)

•Customizable for IP-protocol only.

•On-chip DDR or SSRAM memory controller which can address from 4K Bytes to 4 MB Bytes on chip or 256 MB off chip memories (optional)

•Many trade-offs for some functions performed in hardware or software

•Configurable Packet buffers, session table buffers On-chip or Off-chip memories, attached DDR I/II interface. Depending on system, performance, ASIC/FPGA size requirements-> User Customizable, (optional)

•Interfaces directly to GMII, RGMII, MII external 10/100/ 1000 Mbit Phy interfaces

•Architecture can be scaled up to 10-G bits

•Customizable to handle jumbo frames

•Integrated PCIe x 4 bus interface. x8 and x16 (opt)

•Integrated AMBA 2.0 interface for Local Processor control.

•User programmable/ prioritize-able interrupts

•Performs connection/session management

•Monitors, Stores, Maintains and processes more than 4024 live TCP sessions. Customizable, depending upon on-chip memory availability.

•Extendable to 64K TCP sessions. Internal Memory dependent.

•Wire-speed 2Gbps performance at full duplex

•Multiple TOEs can process up to 256K connections per second

•TCP + IP check sum generation and check performed in hardware in less than 6 clks (30 ns at 200 MHz) vs 1-2 us by typical software TCP-stack

•Connection set up and tear down/termination

•User programmable Session table parameters

•Dedicated set of hardware Timers for each TCP/IP session or customizable for sharing stale sessions.

•Multiple ‘slot storage’ for fragmented packets. More slots allocated when more On-chip Memory available. Self-checking available memory logic. (optional)

•Out of sequence packet detection/storage and Reassembly/Segmentation (optional)

•RDMA- Direct Data placement in Applications buffer at full wire speed without CPU-> reduces CPU’s buffer copy time and utilization by 95%

•Future Proof- Flexible implementation of TCP Offload

•Accommodates future Specifications changes.

•Basic mini API available for ARM architecture. Others OSs/CPUs also available