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TCP Offload Engine- Enhanced for interfacing with S/W TCP stack

IP Vendor: 
Intelop Inc.
IP Target Vendor: 
Altera
IP Code Language: 
Verilog
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3A
Spartan-3A DSP
Spartan-3AN
Spartan-3E
Spartan-II
Spartan-IIE
Spartan/XL
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Virtex
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
Virtex-E
Virtex-E EM
Virtex-II
Virtex-II Pro
IP Description: 

Intelop announces major enhancements to their TCP-Offload Engine SoC IP that also has integrated GEMAC, ARP module and AMBA 2.0 bus and PCIe interface running at 2-Gbps capable of managing thousands of simultaneous TCP sessions

Intelop Corporation, a leading high end IP developer, customization & electronic engineering design services provider, today announced major enhancements to their second generation TCP offload engine SoC solution integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interface running at 2 Gbps sustained rates. The latest enhancements will allow customers to fine tune and achieve significant performance improvements when this TOE hardware in client/server modes is transferring packets in established connections when remote end is running legacy TCP/IP software stacks. It is the only TOE engine that does it and integrates so many functions in hardware. It is a new paradigm and new level of integration in networking hardware acceleration. It implements control plane and data plane processing of TCP/IP in hardware that is at least 20 times faster than TCP/IP software stack.
Intelop designed, verified and implemented this SoC in Altera’s high speed FPGA.
Because of its advanced scalable architecture, it can be customized to implement differentiated features and performance requirements to meet customer’s specifications e.g. misc. protocol processing and monitoring at G-bit line rate, in addition to TCP/IP, ARP module, number of simultaneous connections, TCP/IP performance tuning based upon type of network/traffic and application usage, scalable packet FIFO size, scalable size of Session Management table, Session Parameters, scalable size of direct store Packet memories, integrated DDR/SSRAM controllers, choice of PHY interface - XGMII or Serial and more.

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