Poll

What is your preferred platform for FPGA Design Flow ?:

10 G bit TCP/IP Offload engine

IP Vendor: 
Intelop Inc.
IP Code Language: 
Verilog
IP Type: 
Design
IP Description: 

 • Hardware API: Enables dedicated processing in the FPGA for application specific acceleration

·      Ideal for Very high performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications
·      Fully verified using comprehensive verification methdology for ASIC ports and Network system tested core.
·      Smallest logic foot print; less than 20,000 Xilinx slices, Altera ALMs or 250,000 ASIC gates + on-chip memory
·      Fully integrated 10 G bit high performance Ethernet MAC.
·      Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance.
·      Hardware implementation of TCP/IP stacks’ control plane and data plane.
·      Hardware implementation of ARP protocol processing.
·      Extended ARP table creation, deletion management (optional)
·      Adheres to RFCs; 793, 1500, 1700, 813, 791, 2001
·      ‘Sliding Window’ mechanism implemented in hardware allowing total Flow Control
·      ‘Slow start’ transfer control in hardware
·      Customizable for IP-protocol only.
·      Non-TCP Bypass mode lets all Non TCP/IP related traffic go directly to host interface via user_fifo for TCP/IP software to handle
·      Can be deployed behind a gateway which will respond to Gateway-IP request as opposed to ARP request (optional)
·      On-chip DDR or SSRAM memory controller which can address from 4K Bytes to 4 MB Bytes on chip or 256 MB off chip memories (optional)
·      Simple User Side interface for easy hardware integration or a little more complicated for more power full and controlled ‘Streaming’ data transfers.
·      Many trade-offs for some functions performed in hardware or software
·      Configurable Packet buffers, session table buffers On-chip or Off-chip memories, attached DDR I/II interface. Depending on system, performance, ASIC/FPGA size requirements-> User Customizable, (optional)
·      Interfaces directly to XGMII, 10 G Bit serial interfaces
·      Architecture can be scaled up to 40-G bits
·      Customizable to handle jumbo frames
·      Integrated PLB interface (Xilinx)
·      Integrated AMBA 2.0 interface or MIPs CPU bus for Local Processor control. (opt)
·      User programmable/ prioritize-able interrupts
·      Performs connection/session management
·      Monitors, Stores, Maintains and processes up to 1024 live TCP sessions.  Customizable to implement more, depending upon on-chip memory availability and other FPGA limitations.
·      Extendable to 4K TCP sessions. Internal Memory dependent.
·      Wire-speed 20-Gbps  performance in full duplex
·      Multiple TOEs can process up to 4K connections per second
·      TCP + IP check sum generation and check performed in hardware in less than 6 clks (30 ns at 200 MHz) vs 1-2 us by typical software TCP-stack
·      Connection set up and tear down/termination without CPU involvement.
·      User programmable Session table parameters
·      Dedicated set of hardware Timers for each TCP/IP session (opt) or customizable for sharing one set of common timers for all stale sessions.
·      Multiple ‘slot storage’ for fragmented packets. More slots allocated when more On-chip Memory available. Self-checking available memory logic. (optional)
·      Out of sequence packet detection/storage and Reassembly/Segmentation (optional)
·      Direct Data placement in Applications buffer at full wire speed without CPU-> reduces CPU’s buffer copy time and utilization by 95%
·      Support VLAN mode (optional)
·      Easily customizable for filtering various IP and TCP traffic Protocols, directed towards any port or IP (Ideal for security appliances)
·      Implements Full TCP/IP offload or By-Pass mode. (Optional)
·      Future Proof- Flexible implementation of TCP Offload
·      Accommodates future Specifications changes.
 ·      Basic mini API available for easy integration with Linux/windows. Others OSs/CPUs also available

 INT 10011 is the only SOC that integrates 10G TOE + 10 GEMAC + PLB interfaces in the smallest logic footprint. It is highly flexible that is customizable for layer-3, layer 4-7 network infrastructure and network security systems applications. It is recommended for use in, among others, high performance Servers, NICs, SAN/NAS and data center equipment design applications. It provides key IP building blocks for very high performance 10-Giga bit Ethernet ASIC/ASSP/FPGAs.

INT 10011 has built in advanced architectural flexibility that provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others and customize them for their specific design application.
INT 10011 can process TCP/IP sessions as client/server in mixed session mode and other protocols for Network equipment and in-line network security appliances, simultaneously, at 10-G-bit rate. This relieves the host CPU from costly TCP/IP software related session setup/tear down, data copying and maintenance tasks thereby delivering 4x to 8x TCP/IP network performance improvement when compared with TCP/IP software

Intilop offers a wide range of TOE processing hardware cores for 10-GE to 1-GE applications using PCI Express or embedded system interfaces. TOE products support full TCP offload as well as conventional NIC mode operation (in TCP Bypass Mode) and feature advanced software support (optional) where applications need no modification to take advantage of TOE acceleration.

As an option, it provides easy-to-use frameworks for utilizing the Xilinx Virtex-5/6 and PCIe hardcore enabling rapid and efficient system application development.

The 10 G Bit TOE is based upon the proven and mature patent pending 1 G bit TOE architecture from Intilop corporation.

The same architecture is scalable to 40 G bit.

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook