Poll

What is your preferred platform for FPGA Design Flow ?:

Integer to Floating Point Pipelined Converter

IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Math
IP Supported FPGA Device: 
Cyclone III
Stratix
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
Fully complies with the IEEE 754 specification
Double-word integer input numbers (up to 4 bytes)
Single-precision real output numbers
Simple interface
No programming required
Two levels of pipelining
Full accuracy and precision
Results available at every clock
Fully configurable
Fully synthesizable, static synchronous design with no internal tri-states
Description
The DINT2FP megafunction is a pipelined integer-to-floating-point converter. The input and output number format complies with the IEEE 754 specification. The function supports double-word integers (up to 4 bytes) and single-precision real numbers. The convert operation is pipelined to 2 levels, and the input data is fed in every clock cycle. The first result appears after two clock periods of latency, and subsequent results are available at each clock cycle. The DINT2FP megafunction offers full accuracy and precision."

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook