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ID-BCH - BCH Turbo Encoder

IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
DSP - Digital Signal Processing
IP Description: 

The BCH is a multi-level correction code. It's cyclical and variable in size and it's used to correct the insertion of random errors. It is from the same family as Reed-Solomon and also widely used in FEC mechanisms (foward error correction).

This soft-IP is compatible with the pattern DVBS2, among others. It is capable of processing 1 bit per cycle, working at frequencies above 200Mhz when in FPGAs.

- High performance BCH encoder (Up to 330 Mb/s)
- Up to 12 errors correction capability (t=12)
- Easy to use protocols
- Technology independent (Altera, Xilinx, ASIC)
- Compliant with DVB-S2 and DVB-T (and others) standard

The BCH is a multi-level correction code. It's cyclical and variable in size and it's used to correct the insertion of random errors. It is from the same family as Reed-Solomon and also widely used in FEC mechanisms (foward error correction).

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