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I2S Transmitter

IP Vendor: 
Coreworks
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
Spartan-IIE
Virtex
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-E
Virtex-II
Virtex-II Pro
IP Description: 

"The CWda06 I2S transmitter is an audio interface component designed to output an audio sample stream generated in the well known I2S bus interface originally developed by Philips. The user core may be using an arbitrary clock signal (fclk) to place the parallel audio samples into an asynchronous FIFO. An I2S output stage retrieves the samples from the FIFO at the sample rate Fs, using a master clock frequency mclk=256 Fs to serialize the data and generate the 3 signals which form the I2S bus: the bit clock sclk, the sample rate or left/right clock lrclk and the serial data signal sdata.

Device Family Support
# Virtex-4 FX
# Virtex-4 LX
# Virtex-4 SX
# Virtex-II Pro
# Virtex-II
# Virtex-E
# Virtex
# Spartan-3
# Spartan-IIE

Key Features
# Compliant with the I2S standard.
# Flexible Coreworks Audio Parallel Interface (CWAPI) at the input, which permits bridging to other standard interfaces (SPDIF-AES/EBU, IBM CoreConnectâ„¢ , AMBAâ„¢, etc).
# Double clock domain design: FCLK , a fast system clock unrelated to the sample rate frequency Fs, and MCLK, a master clock of value 256*Fs.
# Supports any sample rate, which is defined by MCLK (384kHz for mclk = 98 MHz).
# Supports up to 24 bits per sample.
# Configurable FIFO depth and width.
# Low power mode when idle."

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