I2S to SPDIF Converter

"The CWda04 is an I2S to SPDIF-AES/EBU digital audio format converter. The CWda04 IP core performs the BMC modulation and the insertion of preambles and control bits in the spdif output signal, according to the SPDIF-AES/EBU standard. The CWda04 converter is enabled for operation when the enable signal is high. The master clock signal (mclk) should be synchronous with the I2S signals and its frequency must be 256X the sample rate frequency Fs. The converter introduces a latency of 1 sample. This latency is used to invert the order of the audio bits from MSB-first in the I2S format to LSB-first in the SPDIF-AES/EBU format. The insertion of control bits in the generated SPDIF-AES/EBU signal is controlled by the ctrl_addr port, and the bits are input to the status, validity and user ports. The insertion of the status bit needs an external ROM, where ctrl_addr is the address and status is the memory output. This means that the nth channel status bit is present at the status input when ctrl_addr equals n. The insertion of the validity and user bits is controlled by the lr_clk signal. These bits must change at each transition of lr_clk and will be included in the frame specified by ctrl_addr. If the user ties all ports to ground, a valid PCM consumer mode SPDIF-AES/EBU stream is obtained, with all user bits set to '0'.

Device Family Support
# Virtex-4 FX
# Virtex-4 LX
# Virtex-4 SX
# Virtex-II Pro
# Virtex-II
# Virtex-E
# Virtex
# Spartan-3
# Spartan-IIE
# Spartan-II

Key Features
# Converts an I2S set of signals into an SPDIF-AES/EBU signal.
# Supports arbitrary sample rates.
# Supports up to 24 bits per sample.
# User defined SPDIF-AES/EBU control bits can be inserted in the SPDIF-AES/EBU signal.
# Reciprocal of the Coreworks CWda03 SPDIF-AES/EBU to I2S converter.
# Low power mode when idle."