HyperTransport

"Features
8-bit, fully integrated HyperTransport™ end-chain interface optimized for the Altera® Stratix® II, Stratix II GX, Stratix, and Stratix GX device families
Packet-based protocol
Dual unidirectional point-to-point links
1.2-V LVDS signaling with 100-Ohm differential impedance
Complies with the HyperTransport I/O Link Specification, Revision 1.03
Up to 16 Gbps throughput (8 Gbps in each direction)
Preliminary Stratix II and Stratix II GX device support for 200, 300, 400, 500 MHz DDR links
Full Stratix and Stratix GX device support for 200, 300, 400 MHz DDR links
Easy-to-use MegaWizard® Plug-In generates parameterized MegaCore® functions for resource-optimized instantiations
Manages HyperTransport interface flow control, optimizing performance and ease of use
Independent buffering for each HyperTransport virtual channel
Automatic handling of HyperTransport ordering rules
Stalling of one virtual channel does not delay other virtual channels (subject to ordering rules)
Flexible parameterized buffer sizes, allowing customization depending on system requirements
User interface has independent interfaces for the HyperTransport virtual channels, allowing independent user logic design
Integrated detection and response to common HyperTransport error conditions, such as cyclic redundancy code (CRC) generation and checking to preserve data integrity
Automatically handles all CSR space accesses
Fully integrated HyperTransport configuration space includes all required configuration space registers and HyperTransport capabilities list registers
32-bit and 64-bit support across all base address registers (BARs)
Hardware verified with HyperTransport interfaces on multiple industry-standard processor and bridge devices
Alliance Semiconductor SP1011
Broadcom BCM1250
PLX HT7520
PMC-Sierra RM9000x2
Application-side interface uses the Altera Atlanticâ„¢ interface standard
Intellectual property (IP) functional simulation models provide cycle-accurate behavioral simulations in industry-standard Verilog HDL and VHDL simulation tools
General Description
The Altera HyperTransport MegaCore function implements high-speed packet transfers between physical (PHY) and link-layer devices, and is fully compliant with the HyperTransport specification. This core allows designers to interface quickly and easily to a wide range of HyperTransport technology enabled devices, including network processors, coprocessors, video chipsets, and ASICs."